1. Field of the Invention
This invention relates to an analog/digital converter (referred to as an "A/D converter") for converting an analog signal to a digital signal and, more particularly, to a serial-parallel A/D converter.
2. Description of the Related Art
A serial-parallel A/D converter is advantageous in that the number of comparators involved can be made less than in a full-parallel A/D converter in which a required number of comparators are connected in parallel. A prior-art example of a serial-parallel A/D converter is illustrated in the block diagram of FIG. 16.
A first (first-stage) sub-A/D converter AD1 and a second (second-stage) sub-A/D converter AD2 in FIG. 16 are both constituted by full-parallel A/D converters. An analog input signal Vin is coarsely A/D-converted (to obtain higher order digital data) by the first sub-A/D converter AD1, after which the resulting digital data is D/A-converted by a D/A converter DAC1 to generate an approximate analog reproduction signal. The difference between the analog input signal Vin and the approximate analog reproduction signal is obtained by a subtractor SUB, the difference is amplified by an amplifier AMP, and the amplified signal is finely A/D-converted by the second sub-A/D converter AD2 (to obtain lower-order digital data).
In actual applications, the device is so adapted as to perform a pipeline operation by inserting sample-and-hold circuits at the various components in order to sample and hold the signals. For the sake of simplicity, however, a description thereof is not given here.
Digital logic 1490 subjects the digital data from the first and second sub-A/D converters AD1and AD2 to necessary processing such as delay, synchronization, digital addition and digital compensation, etc., to thereby obtain the final digital output signal.
As shown in FIG. 16, comparison reference voltages Vref1, Vref2 which enter the respective sub-A/D converters are required in a number equivalent to the number of comparators that construct the sub-A/D converters.
FIG. 17 is a block diagram illustrating the construction of a second prior-art example of a serial-parallel A/D converter. As shown in FIG. 17, the second example of the prior art differs from the first example of the prior art depicted in FIG. 16 in that after the analog input signal Vin is coarsely A/D-converted by the sub-A/D converter AD1 of the first stage, a comparison reference voltage in the vicinity of the analog input signal is produced by the D/A converter DAC1 so that the sub-A/D converter AD2 of the second stage compares this comparison reference voltage with the analog input signal Vin to finely A/D convert the input signal.
More specifically, the second-stage sub-A/D converter AD2 in the first example of the prior art shown in FIG. 16 uses the subtractor SUB to obtain the difference between the analog input signal Vin and the approximate analog reproduction signal, amplifies this difference and compares the amplified signal with the comparison reference voltage. By contrast, in the second example of the prior art shown in FIG. 17, the analog input signal Vin is not amplified and is compared with a finer comparison reference voltage. In the second example of the prior art, subtraction is actually performed between the analog input signal and the comparison reference voltage internally of the comparator. Further, in the second example of the prior art, the comparison reference voltage Vref1 for the first-stage sub-A/D converter AD1 often is supplied by the output of the D/A converter DAC1. (In FIG. 17, the comparison reference voltage Vref1 from the D/A converter DAC1 to the A/D converter AD1 is indicated by the dashed line.)
Hereinafter the construction of the first example of the prior art shall be referred to as a "serial-parallel A/D converter which uses an explicit subtractor", and the construction of the second example of the prior art shall be referred to as a "serial-parallel A/D converter which does not use an explicit subtractor".
FIG. 18 is a block diagram illustrating the construction of a multiple-stage serial-parallel A/D converter according to a third example of the prior art. As shown in FIG. 18, the third example of the prior art is obtained by increasing the number of stages of the serial-parallel A/D converter of the first example of the prior art to three. The number of comparators constructing each sub-A/D converter (of full-parallel type) can be made fewer than in the first example of the prior art.
More specifically, in case of e.g. a 9-bit A/D converter, the sub-A/D converters AD1, AD2 would be constituted by two stages of four bits and five bits in the first example of the prior art shown in FIG. 16, so that the total number of comparators constructing the sub-A/D converters would be 2.sup.4 +2.sup.5 =16+32 =48.
On the other hand, in the third example of the prior art shown in FIG. 18, the sub-A/D converters AD1 to AD3 would be constituted by three stages of three bits each and the total number of comparators constructing the sub-A/D converters would be 2.sup.3 +2.sup.3 +2.sup.3 =8+8+8=24.
A fourth example of the prior art is shown in FIG. 19, which illustrates the construction of a serial-parallel subranging A/D converter proposed in the specification of Japanese Patent Application Laid-Open (KOKAI) No.Hei-6-232747. As shown in FIG. 19, this A/D converter is such that the first-stage sub-A/D converter of the serial-parallel A/D converter described as the first example of the prior art is constituted by a similar serial-parallel A/D converter, and the second-stage sub-A/D converter is further constituted by a similar serial-parallel A/D converter.
In FIG. 19, amplifying means that would be inserted between a subtractor 1703 and a sub-A/D converter 1704, between a subtractor 1707 and a sub-A/D converter 1708, and between a subtractor 1711 and a sub-A/D converter 1712 are omitted. In other words, amplifying means generally are inserted in order to improve precision but are not inserted here.